Analysis challenges and interface physics in silicon nanodevices

Summary form only given. Device reliability is the resultant of various analyses of the design, process and product and understanding innumerable phenomenon to curb the extension of even atomic level defects, especially when the dimensions are at nanometer level. Many of such defects can be traced using the fault localization tools. However these tools have limitations in revealing the actual defects or defect sites at atomic diensions. Tools employing photon, electron and ion beams as well as nanoprobing have been revisited to reveal the limitations and the need for better techniques [1,2]. The necessity at this stage is the capability to compare the real time results from simulation with the analysis results from the tools. Understanding the physical phenomenon with which devices mal-function becomes more difficult and poses higher difficulty in solving both the device and process problems. One of the most important and interesting area is interfaces and understanding the related issues. Two sets of interfaces - one concerning the basic transistor and the other related to interconnects - have shown unassumable problems in device reliability studies. Physical analysis in correlation with electrical characterization in nano devices using ultrathin gate dielectrics depicts certain limitations at the interfaces and some new phenomenon which affects the performance. As the gate dielectric thickness reduces to atomic levels, the modes of conduction in the region itself changes and the structure gets modified which can affect the device reliability [3]. Use of lowK dielectrics for inter-layers and copper for metallization has introduced new phenomenon and modifications in the understanding of electron conduction through local interconnects from a reliability point of view. The thermal management in such devices is an area of concern. Use of new materials like CNTs for interconnect vias may yield better performance [4], but the interfaces have to be thoroughly studied. S- me of the recent studies to understand the conduction mechanisms, microstructural damages, interface interactions as well as the physical effects in the structural integrity in nano silicon devices will be discussed in this talk.