Thin wafer handling and chip to wafer stacking technologies

The semiconductor industry is facing increased challenges implementing Moore´s law. On one hand side, scaling devices is getting increasingly expensive due to the exponential rise in complexity of lithography solutions that are required to support scaling to ever smaller features. On the other hand side, the dimensional gap between the advanced nodes used for the manufacture of future generation electronics devices and on-chip interconnects as compared with the dimensions offered by organic substrates and circuit boards is widening. This is referred to as the “interconnect gap”, [8] which limits the performance that future generation devices may deliver when integrated in end products such as Smart Phones, Tablet Computers and Laptops or high performance stationary computers. In high performance computing, this limitation manifests itself mainly in lack of bandwidth for communication between processor and memory, while in mobile computing applications, this effect is both a bandwidth limitation combined with excessive power used for memory operations. Due to the limited battery capacities available for mobile devices, this limitation will effectively limit adding further functionality to such portable devices in an effort to maintain acceptable battery life.