Simulations and characterizations for stress reduction designs in wafer level chip scale packages

The three-dimensional finite element analysis (FEA) was adopted to study the stress responses for the general design of a wafer level chip scale package (WLCSP) with one under-bump-metallurgy (UBM) layer, one redistribution layer (RDL) and two polymer layers (called 2P2M WLCSP which includes two polymer layers and two metal layers on a passivated wafer), the low cost designs of 2P1M WLCSP (with one RDL and two polymer layers) and 1P1M WLCSP (with one RDL and one polymer layer) in this study. To validate the FEA result, the board level thermal cycling reliability test of 2P2M WLCSP that followed the JEDEC standard was evaluated and both results were well aligned. Through validation and characterization, the finite element model can be further utilized to achieve precise simulations in systematic simulation studies. For the sake of capturing the top significant factors and their corresponding impact levels to the low-k layer, UBM, RDL pad, top and bottom IMC stresses in 2P2M WLCSP designs, the parameters of die, low-k, polymer, RDL, solder ball and PCB were discussed. By observing the presented results, not only can the significant factors that impact the stress responses be investigated but also the suitable parameters that have the best stress reduction designs in 2P2M WLCSP can be determined. This study can effectively serve as design guidelines and provide a good point of reference for significant factor selection analyses and high reliability designs of 2P2M WLCSP.