DocumentCode
671317
Title
Three dimensional compression molding simulation for wafer level packaging
Author
Chih-Chung Hsu ; Wen-Hsin Weng ; Hsien-Sen Chiu ; Rong-Yeu Chang
Author_Institution
Dept. of Chem. Eng., Nat. Tsing-Hua Univ., Hsinchu, Taiwan
fYear
2013
fDate
22-25 Oct. 2013
Firstpage
234
Lastpage
237
Abstract
Wafer-Level Packaging (WLP) refers to the technology of packaging an integrated circuit at wafer level with the advantage of miniaturizing package size, reducing material cost, and fastening throughput. Embedded Wafer Level Packaging (EMWLP) is one of WLP technologies that have benefits of accessibility of conventional wafer-level process equipments. The core process in the EMWLP is to make a molded wafer with fully populated dies embedded via compression molding. Higher accuracy in the chip positioning is required to avoid the die shift problem, which may deteriorate the quality of deposited layer and cause the failure due to the die misalignment. In this study, a 3D CAE simulation tool is proposed to analyze the die shift problem that arises during the wafer molding process in embedded micro wafer level package. The proposed methodology developed in this work accounts for most of the physical phenomena believed to play an important role in an 8 inch mold compound wafer using compression molding. The results demonstrate that all dies are found to be shifting away from the center and die shift increases as the distance from center of the wafer increases. The simulation tool provides a promising simulation solution for the EMWLP process. By using the integrated analysis, molding defects can be easily detected and moldability problems can be improved efficiently to reduce manufacturing cost and design cycle time.
Keywords
compression moulding; wafer level packaging; 3D CAE simulation tool; EMWLP; chip positioning; die shift problem; embedded wafer level packaging; integrated analysis; integrated circuit packaging; microwafer level package; mold compound wafer; size 8 inch; three dimensional compression molding; wafer molding; Compression molding; Encapsulation; Mathematical model; Polymers; Semiconductor device modeling; Solid modeling; Three-dimensional displays;
fLanguage
English
Publisher
ieee
Conference_Titel
Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2013 8th International
Conference_Location
Taipei
ISSN
2150-5934
Type
conf
DOI
10.1109/IMPACT.2013.6706653
Filename
6706653
Link To Document