Title :
Process feasibility of a novel dielectric material in a chip embedded, coreless and asymmetrically built-up structure
Author :
Yin-Po Hung ; Yu-Wei Huang ; Ren-Shin Cheng ; Fang-Jun Leu ; Su-Yu Fun ; Yu-lan Lu ; Tao-Chih Chang
Author_Institution :
Electron. & Optoelectron. Res. Labs., Ind. Technol. Res. Inst. (ITRI), Hsinchu, Taiwan
Abstract :
Chip embedded technology enables advanced integration of modern electronic package structures due to its characteristics of small size, higher performance, lower overall cost and reduction of time to market. Moreover, stacking multiple layers of embedded components can allow an even higher capacity of devices and packaging density. Comparing to 3D interconnection by through silicon via (TSV), device embedded module can have relevant effects by using PCB compatible process though the size and transmitting path is slightly higher than 3D IC modules. However, warpage issue is one of the significant factors that affect the manufacturing of device embedded products due to the asymmetric package form. A strong and robust substrate or core layer, such as high Tg FR4 substrate, BT substrate or Cu lead frame, is often required to provide a stiffening effect for the structure to prevent from severe warpage. In order to acquire even thinner package form, finer L/S specifications, and higher density of interconnection, coreless substrate may be one of the solution to meet the demand. But the asymmetric characteristic of embedded package structure may be regarded as a challenge when applied in coreless structure without a core layer. In this paper, a new type dielectric material with the characteristic of low CTE is disclosed. When it was applied in an asymmetric package structure with embedding chip, warpage behavior was found suppressed comparing to conventional dielectric materials. Moreover, when it was applied in a coreless structure with chip embedded, the structure can still maintain considerable flatness. The process feasibility of laser via forming, Cu plating was evaluated, while tensile strength of the plated Cu and reliability of the laminated structure were examined. An additional PI material was coated as the release layer in the forming of the coreless structure. The concept of asymmetric built-up coreless structure was brought up according to the materials´ cha- acteristics and regarded as a potential solution for 3D System-in-Package in this study.
Keywords :
dielectric materials; electronics packaging; electroplating; integrated circuit interconnections; printed circuits; system-in-package; tensile strength; three-dimensional integrated circuits; 3D system-in-package; BT substrate; Cu lead frame; Cu plating; FR4 substrate; PCB compatible process; asymmetric built-up coreless structure; asymmetric package; asymmetrically built-up structure; chip embedded technology; coreless built-up structure; dielectric material; electronic package; embedded built-up structure; embedded package structure; interconnection; stacking multiple layers; tensile strength; through silicon via; warpage behavior; Dielectric materials; Reliability; Rough surfaces; Substrates; Surface morphology; Surface roughness;
Conference_Titel :
Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2013 8th International
Conference_Location :
Taipei
DOI :
10.1109/IMPACT.2013.6706677