Routing bandwidth model for feed forward neural networks on multicore neuromorphic architectures

Specialized multi-core architectures can provide significant speedups for neural network applications. In this study, we examined the on-chip routing network bandwidth requirements for such architectures processing large multi-layered feed forward neural networks in a pipelined manner. Two on-chip routing network topologies were examined: mesh networks and hybrid bus-mesh networks. Two routing bandwidth models were developed for each network topology: one examined sending neuron outputs from one layer to the next, while the other examined the streaming of synaptic weights from off-chip memory. The model was validated through several simulations studies. For both mesh and bus-mesh interconnection area and power of the on-chip routing network was estimated using the Orion on-chip network tool. Our results show that in multi-core neuromorphic architectures, a bus-mesh interconnection requires less routing area and power compared to a mesh interconnection. We also observed that the accumulated bandwidth requirement in the on-chip network to access off-chip data is much greater than bandwidth required to send neuron outputs between cores.