DocumentCode :
671647
Title :
Correctness and performance of the SpiNNaker architecture
Author :
Sharp, Toby ; Furber, Steve
Author_Institution :
Adv. Processor Technol. Group, Univ. of Manchester, Manchester, UK
fYear :
2013
fDate :
4-9 Aug. 2013
Firstpage :
1
Lastpage :
8
Abstract :
SpiNNaker is a computer architecture designed to simulate many millions of neurons in real-time, using very many low-power processors and biologically inspired communications. This paper demonstrates that prototype SpiNNaker hardware correctly and quickly simulates networks of point neurons with respect to established reference simulators. Models of increasing complexity are presented and the simulation results obtained from SpiNNaker, NEST and Brian are shown to correlate. An execution profile is sketched of real-time simulation on SpiNNaker, and it is shown to outperform NEST using similar computational resources on a standard benchmark model.
Keywords :
computer architecture; neural nets; Brian; NEST; SpiNNaker architecture; biologically inspired communication; computer architecture; low-power processor; neurons; Computational modeling; Correlation; Firing; Neurons; Pipelines; Program processors; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Neural Networks (IJCNN), The 2013 International Joint Conference on
Conference_Location :
Dallas, TX
ISSN :
2161-4393
Print_ISBN :
978-1-4673-6128-6
Type :
conf
DOI :
10.1109/IJCNN.2013.6706988
Filename :
6706988
Link To Document :
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