DocumentCode
67166
Title
Dead-Time Compensation of Inverters Considering Snubber and Parasitic Capacitance
Author
Zhendong Zhang ; Longya Xu
Author_Institution
Dept. of Electr. & Comput. Eng., Ohio State Univ., Columbus, OH, USA
Volume
29
Issue
6
fYear
2014
fDate
Jun-14
Firstpage
3179
Lastpage
3187
Abstract
In power electronics drive systems, dead time is used to prevent shoot-through over power devices. However, dead time can lead to distortion of ac output voltages and currents. Various compensation methods have been proposed to overcome this drawback. However, most strategies assume the power switches as ideal switches and the transition from ON to OFF or vice versa is infinitely fast. In this paper, effects of inverter snubber and parasitic capacitance to the switching instants are investigated when doing dead-time compensation. A new dead-time compensation method is presented with the capacitance being considered. It is verified that the compensation becomes more accurate and effective for the specific application after the modification. It is also shown that the proposed compensation can make the inverter system stable and robust. This proposed approach is validated by the experimental results.
Keywords
PWM invertors; snubbers; PWM inverters; dead-time compensation method; inverter snubber; parasitic capacitance; power electronics drive systems; power switches; pulse-width-modulated inverters; switching instants; Capacitors; Inverters; Parasitic capacitance; Pulse width modulation; Snubbers; Switches; Dead time; pulse shift; pulse-based dead-time compensator (PBDTC); snubber and parasitic capacitance; voltage-second balance;
fLanguage
English
Journal_Title
Power Electronics, IEEE Transactions on
Publisher
ieee
ISSN
0885-8993
Type
jour
DOI
10.1109/TPEL.2013.2275551
Filename
6573390
Link To Document