FPGA-based implementation of channel-blind adaptive equalizers

Inter-Symbol Interference (ISI) is a major obstacle for reliable communication over band-limited or multi-path channels as it results in overlapped symbols at the receiver, and therefore, elevated bit-error rate. This limitation reduces the potential performance gains of high order modulation schemes to be used in modern communication standards. Blind equalization algorithms can solve such problem without the reduction in data rate that is associated with data-aided equalizers. In this paper we propose a Field Programmable Gate Array (FPGA) implementation of adaptive fractionally spaced (FSE) blind equalizer, which is both efficient and scalable. The implementation results are provided and its real-time performance on a 2-by-2 Multi-Input Multi-Output (MIMO) channel using 16-QAM modulation is validated by measuring against simulation results.