Efficient bit-plane implementation for VC1 video decoder for multi-core architecture

VC1 is popular video standard used across many applications ranging from blu-rays disc, internet streaming, broadcast etc. The complexity of VC1 video standard requires typically hardware solution running at macro-block level. Bitplane algorithm is special processing that runs in software at frame level which results that requires higher clocking on hardware due to its inactivity during this time. This paper proposes efficient bit-plane decoding of VC1 in software by using multi-core RISC processors. The proposal uses the pipeline across multiple cores to improve overall software speed. The proposed solution is implemented on TI´s Video engine (IVAHD) in multimedia chips (OMAP & DM series). The proposed solution is up-to 30% faster using two RISC processors and enables 1080p performance in 266 MHz of video hardware engine (IVAHD).