Low power architecture for motion compensation in a 4K Ultra-HD AVC and HEVC video codec system

Motion Compensation in Video Codec is a step where blocks of pixels from Reference Picture are fetched and interpolated to form the prediction image for the current picture being processed. There are several challenges in implementing this functionality in hardware - (1) to identify the minimum set of reference pixels needed to give the required prediction image in an efficient manner from external memory, (2) to fetch these pixels from the external memory at a rate to match the 4K Ultra HD frame processing and (3) to perform the processing in a power optimal manner. This paper describes architecture for motion compensation hardware which integrates command preparation, a 2D reference pixel data caching scheme, a DMA engine and a power efficient pixel interpolation engine. The 2D caching technique helps in reducing the LPDDR2 SDRAM power for a 4k Ultra-HD decoder by up to 70 mW and bandwidth by 800 MB/s (50% reduction), increasing the typical 1080p30 HDMI playback time by 2 hours. The motion compensation hardware module dissipates 3 mW for 1080p30 decode.