DocumentCode
672812
Title
A reconfigurable and scalable verification environment for NoC design
Author
Lim, Z.N. ; Loh, S.H. ; Lee, S.W. ; Yap, V.V. ; Ng, M.S. ; Tang, C.M.
Author_Institution
Univ. Tunku Abdul Rahman (UTAR), Kampar, Malaysia
fYear
2013
fDate
27-28 Nov. 2013
Firstpage
1
Lastpage
4
Abstract
A flexible verification environment is introduced that is adaptive for the corresponding NoC architecture. We will describe the method using the Universal Verification Methodology (UVM) to create a reconfigurable and scalable platform to facilitate the early verification and validation of the NoC system.
Keywords
integrated circuit design; network-on-chip; NoC architecture; NoC design; UVM; flexible verification environment; scalable verification environment; universal verification methodology; Adaptation models; Architecture; Complexity theory; Cryptography; Monitoring; Ports (Computers); Vectors; NoC Verification Environment; Reconfigurable; Scalable;
fLanguage
English
Publisher
ieee
Conference_Titel
New Media Studies (CoNMedia), 2013 Conference on
Conference_Location
Tangerang
Print_ISBN
978-602-8944-21-2
Type
conf
DOI
10.1109/CoNMedia.2013.6708540
Filename
6708540
Link To Document