DocumentCode :
673212
Title :
Design development & performance analysis of high speed comparator for reconfigurable ΣΔ ADC with 180 nm TSMC technology
Author :
Palagiri, HarshaVardhini ; Makkena, MadhaviLatha ; Chantigari, Krishna Reddy
Author_Institution :
Dept. of ECE, V.I.T.S. Deshmukhi, Hyderabad, India
fYear :
2013
fDate :
21-22 Sept. 2013
Firstpage :
1
Lastpage :
6
Abstract :
Comparator design has a crucial influence on the overall performance that can be achieved by Analog to Digital Converter (ADC). The need for programmable analog parts is in research from several years. The ADC´s being mixed signal in nature requires novel architectures to achieve programmability by digital means. The work being carried out aims to bring out architecture of differential pin, which can give better performance when configured as comparator for reconfigurable Sigma Delta ΣΔ ADC, which fulfil an important role in today´s mostly digital mixed-mode systems as interface circuits between the analog world and the powerful digital signal processing. This comparator for a ΣΔ ADC is designed using CMOS 180nm TSMC technology. The simulation is carried out with h-SPICE tool and results prove the circuit operates maximum up to 400 MHz clock speed with gain of 110K. The layout simulation results running up to 250MHz with a gain of 74K agree with the parasitic overhead.
Keywords :
CMOS digital integrated circuits; comparators (circuits); integrated circuit design; sigma-delta modulation; CMOS TSMC technology; analog to digital converter; differential pin architecture; digital mixed-mode systems; digital signal processing; high speed comparator design development; high speed comparator performance analysis; interface circuits; layout simulation; parasitic overhead; reconfigurable sigma delta ΣΔ ADC; size 180 nm; CMOS integrated circuits; Field programmable gate arrays; Integrated circuit modeling; Layout; Semiconductor device modeling; Simulation; Very large scale integration; Analog to DigitalConverter, Digitally programmable Sigma Delta ADC; Edge triggered DFF; comparator;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Computing Technologies (ICACT), 2013 15th International Conference on
Conference_Location :
Rajampet
Print_ISBN :
978-1-4673-2816-6
Type :
conf
DOI :
10.1109/ICACT.2013.6710507
Filename :
6710507
Link To Document :
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