• DocumentCode
    673246
  • Title

    Priority algorithm based VLSI testing technique for BIST

  • Author

    Ganesh, L.K.M. ; Pattanayak, Lopamudra ; Khare, Kavita

  • Author_Institution
    KIIT Univ., Bhubaneswar, India
  • fYear
    2013
  • fDate
    21-22 Sept. 2013
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    The paper presents a low test time BIST based on Priority Algorithm (PA) is applied for the 32-bit Carry Look-Ahead Adder. This method assigns priority to the test patterns based on faulty coverage and independent faulty detecting test patterns. Experiment conducted on Cadences´ RTL Compiler Tool and Cadences´ Encounter Tool demonstrate that proposed scheme gives better performance with large reduction in test time and power dissipation during testing.
  • Keywords
    VLSI; adders; built-in self test; integrated circuit testing; logic testing; BIST; Cadences Encounter Too; Cadences RTL Compiler Tool; carry look-ahead adder; faulty coverage; independent-faulty-detecting test pattern; power dissipation; priority algorithm-based VLSI testing technique; Adders; Built-in self-test; Circuit faults; Integrated circuits; Logic gates; Vectors; BIST; LFSR; Priority Test Patterns; Test Time;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Computing Technologies (ICACT), 2013 15th International Conference on
  • Conference_Location
    Rajampet
  • Print_ISBN
    978-1-4673-2816-6
  • Type

    conf

  • DOI
    10.1109/ICACT.2013.6710542
  • Filename
    6710542
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=673246