DocumentCode
674418
Title
Mechanism for suppression of output voltage distortion of matrix converter by using space vector modulation with improved pulse pattern
Author
Karakama, Hirotaka ; Yamamoto, Koji
Author_Institution
Dept. of Electr. & Electron. Eng., Kagoshima Univ., Kagoshima, Japan
fYear
2013
fDate
26-29 Oct. 2013
Firstpage
1857
Lastpage
1862
Abstract
A modulation method, which consists of conventional space vector modulation (SVM) method based on a virtual AC/DC/AC conversion and carrier signal modulation for matrix converters, was proposed by authors, previously. The proposed SVM method can reduce distortion of output voltage waveforms. In this paper, the proposed SVM method is explained. And a mechanism for suppression of output voltage distortion is examined by the simulation. Specifically, the mechanism for suppression of output voltage distortion is clarified by the analysis of PWM pattern produced from the proposed SVM method. Finally, coincidence of simulation and experimental results confirms the validity of the mechanism.
Keywords
PWM power convertors; matrix convertors; AC-DC-AC conversion; PWM pulse pattern; SVM method; carrier signal modulation; matrix converter; output voltage distortion suppression; space vector modulation method; Load modeling; Matrix converters; Pulse width modulation; Support vector machines; Switches; Vectors; PWM pattern; matrix converter; output voltage distortion; space vector modulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Machines and Systems (ICEMS), 2013 International Conference on
Conference_Location
Busan
Print_ISBN
978-1-4799-1446-3
Type
conf
DOI
10.1109/ICEMS.2013.6713282
Filename
6713282
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