Implementation of heart rate variability signal processing into FPGA: System on-chip design

In this paper, we try to develop and implement the HRV signal processing into a Field Programmable Gate Array (FPGA) for extracting this signals feature. The hardware implementing algorithm was developed in Verilog Hardware Description Language (HDL). In designed hardware, after defining the number of samples in the input, it extracts and analyses the time domain features of HRV signal and also the parameters that can be extracted from the Poincare plot of this signal. The number of 15 recorded HRV signal from the Physionet database (Normal Sinus Rhythm (NSR), Congestive Heart Failure (CHF) and Atrial Fibrillation (AF)) used as test input to test the modules implemented on FPGA. The performance of the system was tested using MATLAB and validated based on the mentioned input signals. Simulations show that the proposed system is able to achieve appropriate HRV analyses in the hardware. This system can be develop and use for more feature extraction by diferent kinds of analysis on HRV signal. The proposed system is suitable for portable monitoring devices and arrhythmia detection and as a biomedical signal processor on a system-on-chip (SOC) design.