A novel dual entropy core true random number generator

True random number generators based on 1D chaotic maps have limited entropy generation capability due to their finite number of Lyapunov exponent(s). In this work, we introduce a novel dual entropy core discrete time chaos based true random number generator architecture that can enhance the randomness of the bitstream using hardware redundancy. We develop a custom mathematical model of the proposed TRNG architecture for numerical simulations and, show that the entropy generated by the proposed architecture is higher than that of a single entropy core counterpart. We calculate the entropy of the generated bitstream using a practical information metric: T-entropy. T-entropy calculations reveal that the proposed architecture is capable of generating high entropy for a wide range of parameter values. As a proof of concept, we implemented the proposed architecture on a field programmable analog array integrated circuit. Acquired random numbers successfully passed all NIST 800.22 statistical tests without any post-processing. To the very best of our knowledge this is the first hardware implementation of a dual entropy core true random number generator in the literature.