Title :
Viterbi Decoders Generation for FPGA Platforms
Author :
Espinosa, Luis Alberto Luna ; De Dios Lopez Sanchez, Juan ; Hipolito, Juan Ivan Nieto ; Vazquez Briseno, Mabel ; Ramos, Aldo E. Perez ; Reyes, Salvador Villareal
Author_Institution :
Univ. Autonoma de Baja California, Baja, CA, USA
Abstract :
In this paper, we describe a relation that allows to generate Viterbi decoders for FPGA platforms. These decoders are created from the vectors that describe the adders of a convolutional encoder with code rate 1/2. This relation has been used to implement a script in Mat lab, which generates decoders in VHDL language for an FPGA platform from a basic set of entities used to create ACS cells.
Keywords :
Viterbi decoding; channel coding; convolutional codes; field programmable gate arrays; hardware description languages; ACS cells; FPGA platforms; Matlab; VHDL language; Viterbi decoders generation; add-compare-select cells; channel codings; convolutional encoder; Communication systems; Convolutional codes; Decoding; Field programmable gate arrays; Measurement; Registers; Viterbi algorithm; FPGA; Viterbi decoder;
Conference_Titel :
Mechatronics, Electronics and Automotive Engineering (ICMEAE), 2013 International Conference on
Conference_Location :
Morelos
Print_ISBN :
978-1-4799-2252-9
DOI :
10.1109/ICMEAE.2013.32
