DocumentCode
674982
Title
ISP: Using idle SMs in hardware-based prefetching
Author
Falahati, Hajar ; Abdi, M. ; Baniasadi, Amirali ; Hessabi, Shaahin
Author_Institution
Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran
fYear
2013
fDate
30-31 Oct. 2013
Firstpage
3
Lastpage
8
Abstract
The Graphics Processing Unit (GPU) is the most promising candidate platform for faster rate of improvement in peak processing speed, low latency and high performance. The highly programmable and multithreaded nature of GPUs makes them a remarkable candidate for general purpose computing. However, supporting non-graphics computing on graphics processors requires addressing several architecture challenges. In this paper, we focus on improving performance by better hiding long waiting time to transfer data from the slow global memory. Thereupon study an effective light-overhead prefetching mechanism, which utilizes idle processing elements. Our results show that we can potentially improve Instruction per Cycle (IPC) up to 8%.
Keywords
graphics processing units; multiprocessing systems; storage management; GPU; IPC; ISP; general purpose computing; graphics processing unit; hardware-based prefetching; idle stream multiprocessors prefetcher; instruction per cycle; light-overhead prefetching mechanism; processing elements; Computer architecture; Graphics processing units; Kernel; Pipelines; Prefetching; GPGPU; Global memory access; Idle processing element utilization; Performance and Energy optimization; Prefetching;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture and Digital Systems (CADS), 2013 17th CSI International Symposium on
Conference_Location
Tehran
Print_ISBN
978-1-4799-0562-1
Type
conf
DOI
10.1109/CADS.2013.6714230
Filename
6714230
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