Title :
Decoder with the dynamic CMOS matrix
Author :
Palocko, Lukas ; Broulim, Jan ; Moldaschl, Jan
Author_Institution :
Fac. of Electr. Eng., Univ. of West Bohemia, Pilsen, Czech Republic
Abstract :
This paper presents the Full Custom Design technique in the IC digital design, which is used to achieve the maximum performance or minimum power. The technique was applied on the decoder of the ARM1 register file. Presented research combines a static CMOS logic and a dynamic logic, which has higher speed than the equivalent static family. The validation of the design is made by the SPICE3 simulator (BSIM3 model) considering RC parasitic values of metal wiring. Our results demonstrate the size of the register file decoder and behavior of the dynamic matrix.
Keywords :
CMOS logic circuits; decoding; flip-flops; integrated circuit design; logic design; ARM1 register; BSIM3 model; IC digital design; RC parasitic values; SPICE3 simulator; dynamic CMOS matrix; dynamic logic; full custom design technique; metal wiring; register file decoder; static CMOS logic; CMOS integrated circuits; Computer architecture; Decoding; Layout; Metals; Registers; Transistors; ARM; decoder; dynamic CMOS matrix; register file;
Conference_Titel :
Telecommunications Forum (TELFOR), 2013 21st
Conference_Location :
Belgrade
Print_ISBN :
978-1-4799-1419-7
DOI :
10.1109/TELFOR.2013.6716305
