Title :
Fine grained 3D cache architecture using high density TSVs
Author :
Miro-Panades, Ivan
Author_Institution :
CEA-LETI, MINATEC, Grenoble, France
Abstract :
This article consists of a collection of slides from the author´s conference presentation. Some of the specific areas/topics discussed include: 3D cache architecture; 3D technology TSV and chip-to-chip connection; and physical implementation.
Keywords :
cache storage; integrated circuit interconnections; integrated memory circuits; three-dimensional integrated circuits; 3D technology; chip-to-chip connection; fine grained 3D cache architecture; high density TSV; physical implementation; Cloud computing; Computer architecture; Conferences; Context; Three-dimensional displays; Through-silicon vias; Throughput;
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013 IEEE
Conference_Location :
Monterey, CA
DOI :
10.1109/S3S.2013.6716517
