Fin width scaling for improved short channel control and performance in aggressively scaled channel length SOI finFETs

Author

Paul, A. ; Chun-Chen Yeh ; Standaert, T. ; Johnson, J.B. ; Bryant, A. ; Tripathi, N. ; Tsutsui, G. ; Yamashita, Takayoshi ; Basker, Veeraraghvan S. ; Faltermeier, J. ; Jin Cho ; Huiming Bu ; Khare, Manish

Author_Institution

Technol. Res., GLOBALFOUNDRIES Inc., Albany, NY, USA

fYear

2013

fDate

7-10 Oct. 2013

Firstpage

1

Lastpage

2

Abstract

This work presents SOI finFETs with fin width (Dfin) scaled to sub 15nm. The process flow provides robust Dfin scaling as depicted by the universal electrostatic scaling of the DIBL and sub-threshold swing (SS). The high field long channel mobility drops by ~6% with Dfin scaling, however, DIBL and SS improves by ~1.5X and ~2X, respectively, for 20nm channel length n/pfinFETs. The effective current (Ieff) at fixed Ioff improves by ~20% and ~30% for p and n finFETs, respectively, with Dfin scaling.

Keywords

MOSFET; semiconductor device manufacture; silicon-on-insulator; DIBL; aggressively scaled channel length SOI finFET; drain induced barrier lowering; long channel mobility; process flow provides; robust fin width scaling; short channel control; silicon-on-insulator; subthreshold swing; universal electrostatic scaling; Electrostatics; FinFETs; Logic gates; Market research; Performance evaluation; Process control; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013 IEEE

Conference_Location

Monterey, CA

Type

conf

DOI

10.1109/S3S.2013.6716521

Filename

6716521