Title :
Robust clock tree using single-well cells for multi-VT 28nm UTBB FD-SOI digital circuits
Author :
Giraud, Bastien ; Noel, J.P. ; Abouzeid, Fady ; Clerc, Sylvain ; Thonnart, Yvain
Author_Institution :
CEA LETI MINATEC, Grenoble, France
Abstract :
The 28nm UTBB FD-SOI design platform enables multi-VT standard cells co-integration with independent back biases (BB). In this paper, we propose a new clock-tree cell to build a robust clock tree isolated from the various BB of the different Vt regions, showing better propagation and transition times balancing (2.5x), and a drastic skew reduction (5x at 0.4V) compared to a conventional clock tree.
Keywords :
clocks; digital circuits; elemental semiconductors; network synthesis; silicon; silicon-on-insulator; BB; Si; clock tree cell; drastic skew reduction; independent back biasing; multiVT UTBB FD-SOI digital circuit design; multiVT standard cell cointegration; propagation time balancing; single-well cell; size 28 nm; transition time balancing; Clocks; MOS devices; Propagation delay; Robustness; Standards; Timing; Vegetation;
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013 IEEE
Conference_Location :
Monterey, CA
DOI :
10.1109/S3S.2013.6716540
