Title :
Gate length scaling of high-k vertical MOSFET toward 20nm CMOS technology and beyond
Author :
Sasaki, T. ; Endoh, Tetsuo
Author_Institution :
Grad. Sch. of Eng., Tohoku Univ., Sendai, Japan
Abstract :
This paper presents the gate length scaling of the Vertical MOSFET (VMOS) with high-k dielectrics for beyond 20nm CMOS technology in comparison with Double Gate MOSFET (DG) at the same Drain Induced Barrier Lowering (DIBL). The VMOS can significantly suppresses DIBL within 11mV/V caused by fringing electric field through thicker designed high-k dielectrics (EOT=1.0nm). Moreover, the VMOS can be designed by shorter gate length from 5.4 to 19nm as using higher gate dielectric constant from k=10 to k=60.
Keywords :
CMOS integrated circuits; MOSFET; CMOS; drain induced barrier lowering; electric field; gate length scaling; high-k dielectrics; high-k vertical MOSFET; size 20 nm to 5.4 nm; Capacitance; Dielectric constant; Electric fields; High K dielectric materials; Logic gates; MOSFET;
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013 IEEE
Conference_Location :
Monterey, CA
DOI :
10.1109/S3S.2013.6716557
