An ultra-fast floating-body/gate cell for embedded DRAM

Floating-body DRAM cells (FBCs) on SOI are of interest because of integration problems associated with the large storage capacitor of nanoscale conventional 1T/ 1C DRAM. However, limitations on FBC speed, due to relatively slow write times governed by the usual impact-ionization or tunneling body-charging processes, preclude the application of most interest - embedded DRAM. We recently proposed a novel 2T (T1 and T2) FBC, i.e., a floating-body/gate cell (FBGC) , which enables design flexibility for optimizing performance. We present herein a new 2T design concept (FBGC4) that gives ultra-fast write times, in addition to good current-signal margin and long retention times, and thus enables the embedded-DRAM application. Further, low power and good reliability are implied because of low-voltage operation afforded by FBGC4.