Back bias influence on analog performance of pTFET

In this work the back bias influence on the analog performance of tunnel-FETs is evaluated experimentally for the first time. The analysis of the transconductance, output conductance and intrinsic voltage gain (Av) was performed by comparing the pTFET behavior with a well-known pFinFET that was fabricated using the same process flow. Numerical simulations were also performed in order to explain the pTFET behavior. Although the pTFET shows to be more susceptible to the back bias condition, it also shows to present always a better Av for all bias conditions. The best result in both devices was obtained when the back bias is near 0 V and the Av difference is around 30 dB in favor of pTFET.