Dynamic Time Warping Algorithm: A Hardware Realization in VHDL

The Dynamic Time Warping (DTW) algorithm is a well-known algorithm in matching time sequence data and is used in many applications that require pattern matching. Though computationally intensive, DTW is very effective. In this work, a hardware design for a DTW processing unit in VHDL is proposed, with an objective of further developing systems consisting of multiple units. Simulation studies using MATLAB and FPGA tools show that this basic DTW unit provides an effective and efficient way to compare two time sequences. Space and time analyses are provided to investigate the hardware´s speedup over software and its scalability.