• DocumentCode
    676342
  • Title

    Dynamic Stencil: Effective exploitation of run-time resources in reconfigurable clusters

  • Author

    Xinyu Niu ; Coutinho, J.G.F. ; Yu Wang ; Luk, Wayne

  • Author_Institution
    Dept. of Comput., Imperial Coll. London, London, UK
  • fYear
    2013
  • fDate
    9-11 Dec. 2013
  • Firstpage
    214
  • Lastpage
    221
  • Abstract
    Computing nodes in reconfigurable clusters are occupied and released by applications during their execution. At compile time, application developers are not aware of the amount of resources available at run time. Dynamic Stencil is an approach that optimises stencil applications by constructing scalable designs which can adapt to available run-time resources in a reconfigurable cluster. This approach has three stages: compile-time optimisation, run-time initialisation, and run-time scaling, and can be used in developing effective servers for stencil computation. Reverse-Time Migration, a high-performance stencil application, is developed with the proposed approach. Experimental results show that high throughput and significant resource utilisation can be achieved with Dynamic Stencil designs, which can dynamically scale into nodes becoming available during their execution. When statically optimised and initialised, the Dynamic Stencil design is 1.8 to 88 times faster and 1.7 to 92 times more power efficient than reference CPU, GPU, MaxGenFD, Blue Gene/P, Blue Gene/Q and Cray XK6 designs; when dynamically scaled, resource utilisation of the design reaches 91%, which is 1.8 to 2.3 times higher than their static counterparts.
  • Keywords
    field programmable gate arrays; logic design; optimising compilers; resource allocation; Blue Gene/P; Blue Gene/Q; Cray XK6 designs; FPGA; GPU; MaxGenFD; application developers; compile-time optimisation; dynamic stencil designs; reconfigurable clusters; reference CPU; resource utilisation; reverse-time migration; run-time initialisation; run-time resources; run-time scaling; scalable designs; stencil applications; Bandwidth; Computational modeling; Delays; Field programmable gate arrays; Kernel; Optimization; Parallel processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field-Programmable Technology (FPT), 2013 International Conference on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-1-4799-2199-7
  • Type

    conf

  • DOI
    10.1109/FPT.2013.6718356
  • Filename
    6718356