Title :
A semi-insulation structure for integrating vertical DMOS in smart power integrated circuits
Author :
Kui Ma ; Fa-shun Yang ; Jie-xin Lin ; Xing-hua Fu
Author_Institution :
Dept. of Electron., Guizhou Univ., Guiyang, China
Abstract :
A semi-insulation structure was proposed for high block voltage for vertical DMOS power devices. A smart power integrated circuit (SPIC) was designed and fabricated. The tested result of D-S block voltage of vertical DMOS is about 120V. The breakdown voltage of the isolation structure is about 129V.
Keywords :
integrated circuit reliability; power MOSFET; power integrated circuits; semiconductor device breakdown; semiconductor device reliability; SPIC; breakdown voltage; integrating vertical DMOS; semi-insulation structure; smart power integrated circuits; vertical DMOS power devices; voltage 120 V; voltage 129 V; Dielectrics; Educational institutions; Epitaxial growth; Epitaxial layers; Junctions; Substrates; reliability; semi-insulatin structure; vertiacl DMOS;
Conference_Titel :
TENCON 2013 - 2013 IEEE Region 10 Conference (31194)
Conference_Location :
Xi´an
Print_ISBN :
978-1-4799-2825-5
DOI :
10.1109/TENCON.2013.6718525
