A high speed low noise CMOS dynamic full adder cell

Author

Meher, Preetisudha ; Mahapatra, Kamala Kanta

Author_Institution

Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Rourkela, India

fYear

2013

fDate

27-28 Dec. 2013

Firstpage

1

Lastpage

4

Abstract

A new low power dynamic CMOS one bit full adder cell is presented. In this design technique is based on semi-domino logic. This new cell is compared with some previous proposed widely used dynamic adders as well as other conventional architectures. Objective of this work is to inspect the power, delay, power-delay-product and leakage performance of low voltage full adder cells in different CMOS logic styles. The proposed style gets its benefit in terms of power, delay, PDP, and noise tolerance. The performance of the full adder circuits is based on UMC 180nm CMOS process models at the supply voltage of 1.8V evaluated by the comparison of the simulation results obtained from Cadence.

Keywords

CMOS logic circuits; adders; low-power electronics; CMOS logic styles; Cadence; PDP; UMC CMOS process models; high speed low noise CMOS dynamic full adder cell; leakage performance; low power dynamic CMOS one bit full adder cell; noise tolerance; power-delay-product; semidomino logic; size 180 nm; voltage 1.8 V; Adders; CMOS integrated circuits; Layout; MOS devices; Noise; Transistors; Very large scale integration; Delay; Domino logic; Dynamic logic; Full adder; Power consumption; Power-delay-product; semi-domino adder;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits, Controls and Communications (CCUBE), 2013 International conference on

Conference_Location

Bengaluru

Print_ISBN

978-1-4799-1599-6

Type

conf

DOI

10.1109/CCUBE.2013.6718575

Filename

6718575