FPGA implemented reduced Ethernet MAC

This paper presents an implementation of a reduced Ethernet MAC. The reduced MAC is simple and not resource wasteful. Therefore it is suitable to every project which includes network communication. It is especially useful to low performance FPGAs. In practice, the FPGA boards are well applicable to implement network protocols because the implemented protocols will work in parallel. The main topics of the article cover the base concept of the reduced MAC, the implemented network protocols and the characteristics.