Drive matching issues in multi gate CMOS inverter

In nanowire CMOS design matching n-FET and p-FET current drive and threshold voltage for symmetric performance is a challenging problem. In this paper, we investigate different approaches to match the n- and p-FET drives in silicon nanowire (Si-NW) CMOS inverter. Device design parameters: gate length (L_G), number of nanowire (N_NW), wire diameter (D_NW) and source/drain (S/D) implantation dose (Φ) are used as drive tuning parameters to match the n-FET and p-FET drives. We find that in comparison to use of L_G or N_NW as tuning parameters, the D_NW or Φ tuned CMOS inverters provide significant reduction in circuit active area and active power dissipation. However, the increase of D_NW in p-FET required to match the n-FET drive results in a large amount of increase in leakage current in D_NW tuned CMOS as compared to Φ tuned NW CMOS inverter. Also, it is found that the effect of process variation on NW device performance is more sensitive with D_NW as compared to Φ. It is seen that among all methods, Φ tuned NW CMOS has better overall performance. When compared with the conventional matching approach (multi-NW in p-FET to match the n-FET drive), the Φ tuned NW CMOS inverter shows 38% saving in active power dissipation, and 28% saving in the active area. Hence, Φ tuned NW CMOS inverter is an excellent option for low power applications in Si-NW technology.