Title :
SAO in CTU decoding loop for HEVC video decoder
Author :
Subramanya, Prashanth Nandalike ; Adireddy, Ramakrishna ; Anand, Dhananjay
Author_Institution :
Digital Signal Process. - Software, PathPartner Technol. Consulting Pvt. Ltd., Bangalore, India
Abstract :
In this paper, we present a design for moving Sample Adaptive Offset filter (SAO) inside the Coding Tree Unit (CTU) decoding loop for High Efficiency Video Codec (HEVC) decoder. According HEVC standard & its Test Model (HM) implementation by Joint Collaborative Team - Video Coding (JCT-VC), SAO filtering operation is performed only at frame level. But majority of the applications in which low latency is a requirement, it is necessary to execute SAO filtering at CTU level along with other decoding modules. Executing SAO operation at same granularity as in other decode modules, results in better memory-bandwidth efficiency and cache performance. One other important case where in which CTU level execution of all decode modules, including SAO operation, is a strong requirement is for hardware accelerator based codecs. Suppose if any Application Specific Integrated Circuit (ASIC) to be developed for HEVC, all decode modules are very much expected to execute at same granularity. Most likely the chosen granularity would be CTU/Coding Unit (CU) level due to optimal pipeline performance. In the case of real time applications such as live streaming or video conferencing, keeping SAO filtering module at frame level is not suitable as it will drastically increase the latency and affect overall performance of the codec. In order to alleviate the problems caused by frame level SAO execution and to fulfill all above mentioned requirements, we propose a low-complexity approach to accomplish SAO operation at CTU level/loop. Our proposed method will be very efficient for pipelined architecture in multi-core scenarios. Here SAO filtering in CTU loop has been implemented for HEVC decoder and compared with SAO execution in frame level with and without a frame level pipeline for SAO in a multi-core scenario. The results lead to the conclusion that proposed method is a better alternative to executing SAO in frame level with or without frame level pipeline.
Keywords :
adaptive filters; application specific integrated circuits; multiprocessing systems; video coding; ASIC; CTU decoding loop; HEVC video decoder; JCT-VC; SAO filtering module; SAO filtering operation; application specific integrated circuit; cache performance; coding tree unit; decoding modules; high efficiency video codec; joint collaborative team-video coding; live streaming; memory bandwidth efficiency; multicore scenarios; optimal pipeline performance; pipelined architecture; sample adaptive offset filter; video conferencing; Bandwidth; Decoding; Filtering; Memory management; Multicore processing; Standards; Video coding; CTU Decoding; De-block; HEVC/H265; In-loop filter; Low Latency; Memory Bandwidth; Sample Adaptive Offset (SAO);
Conference_Titel :
Signal Processing and Communication (ICSC), 2013 International Conference on
Conference_Location :
Noida
Print_ISBN :
978-1-4799-1605-4
DOI :
10.1109/ICSPCom.2013.6719845