Multilevel decomposition Discrete Wavelet Transform for hardware image compression architectures applications

In this paper, flexible hardware architecture of multi-level decomposition Discrete Wavelet Transform (DWT) is proposed for image compression applications to eliminate redundant information from the transmitted images or video frames over the wireless channel. This architecture of DWT is described and synthesized with the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) based methodology. The design can be accommodated on any targeting Field Programmable Gate Array (FPGA) device with slight changes. It facilitates to images of size 64×64, 128×128, 256×256, and 512× 512 pixels and capable of seven levels of decomposition. In order to reduce computational complexities, Fast Haar Wavelet Transform (FHWT) is used. The reduction in the resource usage of this 2D DWT multilevel FPGA core can be used to counter severe hardware constraints of various wireless and mobile device applications.