Cycle time variance minimization for WIP balance approaches in wafer fabs

Although work-in-process (WIP) balance approaches can achieve average cycle time reduction, due to the characteristics of wafer fabrication facilities (wafer fabs), e.g., re-entrant flow, setup time and batch processing, a lack of effective mechanism to ensure lot movement at the right pace results in degraded cycle time variance, which might be a potential problem when due date is concerned. This paper attempts to solve this problem. Firstly four cycle time variance minimization rules which utilize waiting time, cycle time and due date information of lot are investigated. Then they are incorporated into two WIP balance approaches in literature to figure out whether they can overcome the drawback arising from WIP balance. In the end the benefit of cycle time variance minimization is illustrated by one example to address an improved ability to meet due date reliably.