Low power analysis of MAC using modified booth algorithm

Multipliers with high speed are essential of digital applications for example signal processing. A new architecture of multiplier-and-accumulator (MAC) was proposed for high-speed arithmetic. By combining multiplication with accumulation the performance was improved. In Modified booth algorithm technique the modified booth encoder will reduce the number of partial products. Even in general purpose processors high speed multipliers are most required to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power. This paper proposes the spurious power suppression technique (SPST) in VLSI will reduce the power consumption of the system significantly.