FPGA implementation for generation of six phase pulse compression sequences

Pulse Compression technique is most widely used in Radar signal processing applications. For better Pulse Compression, peak signal to side lobe ratio i.e. Merit factor should be as high as possible so that the unwanted clutter gets suppressed. To achieve this, Phase Coded Pulse Compression sequences are widely used. The simple phase code is obtained from the Binary Pulse compression sequences but matched filtering of radar signals creates unwanted side lobes which may mask important information. The study of Poly Phase Pulse Compression sequences is carried out since these sequences have low side lobes and are better Doppler tolerant. When we move from Binary to Ternary and Ternary to Six Phase Pulse Compression VLSI systems, the memory requirements are increased, there by the area is increased and the real time implementation needs optimization of speed, area and power consumption. The paper concentrates on the design of an optimized model which can reduce these constraints. The proposed FPGA implementation can efficiently generate Six Phase Pulse Compression sequences while improving some of the parameters like area and speed when compared to previous methods. This module is implemented on FPGA as it provides the flexibility of re-configurability and reprograms ability.