Spatio-temporal scheduling for 3D reconfigurable & multiprocessor architecture

Author

Quang-Hai Khuat ; Quang-Hoa Le ; Chillet, Daniel ; Pillement, Sebastien

Author_Institution

IRISA/INRIA, Univ. of Rennes 1, Rennes, France

fYear

2013

fDate

16-18 Dec. 2013

Firstpage

1

Lastpage

6

Abstract

This article proposes a spatio-temporal scheduling algorithm for a three-dimensional integrated circuits (3D ICs) defined by stacking an homogeneous embedded Field-Programmable Gate Array (eFPGA) above an homogenous Chip MultiProcessor (CMP) layer over through-silicon vias (TSVs) connection. Our proposal, based on Proportionate-fair (Pfair) algorithm, computes the spatio-temporal scheduling of hardware tasks on the reconfigurable resources by taking into account the communication between tasks and then places the associated software tasks on the multiprocessors layer. Compared to the “equivalent” solutions produced by the recursive Branch and Bound (BB) algorithm, our proposal shows up to 14,5% communication cost reduction.

Keywords

field programmable gate arrays; microprocessor chips; three-dimensional integrated circuits; 3D IC; 3D reconfigurable architecture; BB algorithm; CMP layer; Pfair algorithm; TSV connection; eFPGA; hardware tasks; homogeneous embedded field-programmable gate array; homogenous chip multiprocessor layer; multiprocessor architecture; proportionate-fair algorithm; recursive branch and bound algorithm; software tasks; spatiotemporal scheduling algorithm; three-dimensional integrated circuits; through-silicon vias connection; Computer architecture; Hardware; Program processors; Receivers; Scheduling; Three-dimensional displays; 3D architecture; Pfair; multiprocessors; reconfigurable dynamique; spatio-temporal scheduling;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test Symposium (IDT), 2013 8th International

Conference_Location

Marrakesh

Type

conf

DOI

10.1109/IDT.2013.6727131

Filename

6727131