DocumentCode
679447
Title
Mixed-Criticality Scheduling upon Varying-Speed Processors
Author
Baruah, Sunandan ; Zhishan Guo
Author_Institution
Univ. of North Carolina at Chapel Hill, Chapel Hill, NC, USA
fYear
2013
fDate
3-6 Dec. 2013
Firstpage
68
Lastpage
77
Abstract
A varying-speed processor is characterized by two execution speeds: a normal speed and a degraded speed. Under normal circumstances it will execute at its normal speed, conditions during run-time may cause it to execute more slowly (but no slower than at its degraded speed). The problem of executing an integrated workload, consisting of some more important components and some less important ones, upon such a varying-speed processor is considered. It is desired that all components execute correctly under normal circumstances, whereas the more important components should execute correctly (although the less important components need not) if the processor runs at any speed no slower than its specified degraded speed.
Keywords
processor scheduling; degraded speed; mixed-criticality scheduling; normal speed; varying-speed processor; Clocks; Degradation; Processor scheduling; Program processors; Real-time systems; Schedules; Scheduling;
fLanguage
English
Publisher
ieee
Conference_Titel
Real-Time Systems Symposium (RTSS), 2013 IEEE 34th
Conference_Location
Vancouver, BC
ISSN
1052-8725
Type
conf
DOI
10.1109/RTSS.2013.15
Filename
6728862
Link To Document