Title :
Hardware accelerated protein inference framework
Author :
Vidanagamachchi, S.M. ; Dewasurendra, S.D. ; Ragel, R.G.
Author_Institution :
Univ. of Peradeniya, Peradeniya, Sri Lanka
Abstract :
Protein inference plays a vital role in the proteomics study. Two major approaches could be used to handle the problem of protein inference; top-down and bottom-up. This paper presents a framework for protein inference, which uses hardware accelerated protein inference framework for handling the most important step in a bottom-up approach, viz. peptide identification during the assembling process. In our framework, identified peptides and their probabilities are used to predict the most suitable reference protein cluster for a given input amino acid sequence with the probability of identified peptides. The framework is developed on an FPGA where hardware software co-design techniques are used to accelerate the computationally intensive parts of the protein inference process. In the paper we have measured, compared and reported the time taken for the protein inference process in our framework against a pure software implementation.
Keywords :
biological techniques; field programmable gate arrays; hardware-software codesign; molecular biophysics; probability; proteins; proteomics; FPGA; amino acid sequence; bottom-up approach; hardware accelerated protein inference framework; hardware software co-design techniques; peptide identification; probability; protein cluster; proteomics; software implementation; top-down approach; Acceleration; Field programmable gate arrays; Hardware; Peptides; Proteins; Software; Tiles; Aho-Corasick FPGA; Protein Inference;
Conference_Titel :
Industrial and Information Systems (ICIIS), 2013 8th IEEE International Conference on
Conference_Location :
Peradeniya
Print_ISBN :
978-1-4799-0908-7
DOI :
10.1109/ICIInfS.2013.6732061