DocumentCode :
680049
Title :
A delay-based PUF design using multiplexer chains
Author :
Miaoqing Huang ; Shiming Li
Author_Institution :
Dept. of Comput. Sci. & Comput. Eng., Univ. of Arkansas, Fayetteville, AR, USA
fYear :
2013
fDate :
9-11 Dec. 2013
Firstpage :
1
Lastpage :
6
Abstract :
Physically unclonable functions (PUFs) have been a hot research topic in hardware-oriented security for many years. Given a challenge as an input to the PUF, it generates a corresponding response, which can be treated as a unique fingerprint or signature for authentication purpose. In this paper, a delay-based PUF design involving multiplexers on FPGA is presented. Due to the intrinsic difference of the switching latencies of two chained multiplexers, a positive pulse may be produced at the output of the downstream multiplexer. This pulse can be used to set the output of a D flip-flop to `1´. Further, it is proposed to directly incorporate challenge bits into the primitive PUF design to bring another layer of randomness for the response. Evaluation results on various devices and under different operating temperatures demonstrate the applicability of the proposed PUF design.
Keywords :
cryptography; field programmable gate arrays; logic design; multiplexing equipment; FPGA; delay-based PUF design; downstream multiplexer; hardware-oriented security; multiplexer chains; physically unclonable functions; positive pulse; switching latency; two chained multiplexers; Field programmable gate arrays; Hamming distance; Multiplexing; Niobium; Shift registers; Switches; Table lookup;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on
Conference_Location :
Cancun
Print_ISBN :
978-1-4799-2078-5
Type :
conf
DOI :
10.1109/ReConFig.2013.6732258
Filename :
6732258
Link To Document :
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