An effective window based legalization algorithm for FPGA placement

Placement is one of the most important techniques in modern field-programmable gate array design. Generally, analytical placement method optimizes the wire-length in global stage while allowing overlaps between blocks and is followed by a legalization step to remove all overlaps. In this paper, we propose a window based legalization method to remove all overlaps and place all instances at legalized locations based on the architecture of the given field-programmable gate array. The experimental results show that our window based legalization method produces significantly better results than a conventional greedy method in terms of wire-length, total displacements, and CPU time.