Automated design flow for no-cost configuration error detection in sram-based FPGAs

Soft errors in the configuration memory of SRAM-based FPGAs cause significant and remanent application disturbances. However, classical mitigation techniques based on massive redundancy are too costly for most applications. The method presented in this paper is based on selective redundancy in partially used LUTs. It can be applied so that no hardware is added at the system level and it has been automated in standard design flows for Xilinx and Altera families. The detection of soft errors in the configuration is performed within one clock period. Experimental results on benchmark implementations are discussed, showing the good ratio between coverage and block-level overheads, with almost no impact on power and delay. The differences between applying the approach to Virtex V and Stratix IV devices are also discussed.