Energy-efficient Median filter on FPGA

Median filters are a popular method for noise extraction, with much work done in the community to achieve high throughput and low hardware cost. In contrast, energy efficiency remains an untapped area for improvement though it has become a topic of increasing interest. We deduce memory to be the main contributing factor through energy consumption analysis of our median filter architecture. To lower memory energy demands, we use a memory activation scheduling technique, developing an optimal schedule for memory blocks and enabling the minimum number of blocks required each cycle, while deactivating the other blocks. We implement our median filter architecture on a state-of-the-art FPGA to evaluate the performance, using image sizes from 128 × 128 to 1024 × 1024 pixels with standard pixel depths of 8 bpp, 16 bpp, 24 bpp and 32 bpp. Our implementation has up to 53 % of the peak performance of the target device. The post place-and-route results show that our energy-optimized median filter implementation has an average of 4.0× higher energy efficiency in comparison with the baseline architecture with fully-enabled memory and can maintain at least 400 frames/s for a 512 × 512 image for any pixel depth.