Parallel and configurable turbo decoder implementation for 3GPP-LTE

Author

Gonzalez-Perez, Luis F. ; Yllescas-Calderon, Lennin C. ; Parra-Michel, R.

Author_Institution

Res. Center for Electron. Design ITESM, Guadalajara, Mexico

fYear

2013

fDate

9-11 Dec. 2013

Firstpage

1

Lastpage

6

Abstract

An FPGA implementation of a highly parallel and configurable architecture for turbo decoding, compliant with the 3GPP-LTE standard is presented. This architecture can be integrated in reconfigurable platforms for software defined radio applications. A novel combination of the next iteration initialization method and the parallel and sliding window techniques is used in the MAP algorithm. This allows high throughput and reduced storage requirements, as compared to other solutions. Synthesis results on Altera FPGAs show that this architecture can reach 337.6 Mbps at 8 decoding iterations.

Keywords

3G mobile communication; Long Term Evolution; field programmable gate arrays; iterative methods; parallel processing; telecommunication computing; turbo codes; 3GPP-LTE standard; FPGA implementation; configurable turbo decoder implementation; decoding iterations; iteration initialization method; parallel techniques; parallel turbo decoder implementation; reconfigurable platforms; sliding window techniques; software defined radio applications; Computer architecture; Decoding; Hardware; Iterative decoding; Measurement; Throughput; Turbo codes; 3GPP-LTE; MAP decoder; QPP interleaving; Software Defined Radio; VLSI; parallel turbo decoding;

fLanguage

English

Publisher

ieee

Conference_Titel

Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on

Conference_Location

Cancun

Print_ISBN

978-1-4799-2078-5

Type

conf

DOI

10.1109/ReConFig.2013.6732316

Filename

6732316