DocumentCode :
680106
Title :
A tiny RSA coprocessor based on optimized systolic Montgomery architecture
Author :
Liu, Zongbin ; Xia, Luning ; Jing, Jiwu ; Liu, Peng
Author_Institution :
The State Key Laboratory of Information Security, Graduate University of Chinese Academy of Sciences, Beijing, China
fYear :
2011
fDate :
18-21 July 2011
Firstpage :
105
Lastpage :
113
Abstract :
In this paper we propose a new hardware architecture of modular exponentiation, which is based on the optimized Montgomery multiplication. At CHES 1999, Tenca introduced a new architecture for implementing the Montgomery multiplication which was later improved by Huang et al. at PKC 2008. In this paper we improve the architecture of Huang and the improved one occupies less hardware resource, at the same time we add the final subtraction of the Montgomery algorithm into the architecture in order to do the exponentiation computation. Finally we use this improved architecture to build a RSA coprocessor. Compared with the previous work, the new 1024-bit RSA coprocessor saved nearly 50% of area, and the area utilization is greatly improved. This design is the smallest design as we know in the literature, and we verified the correctness by huge test data.
Keywords :
Adders; Algorithm design and analysis; Clocks; Computer architecture; Coprocessors; Cryptography; Embedded systems; FPGA; Montgomery; RSA;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Security and Cryptography (SECRYPT), 2011 Proceedings of the International Conference on
Conference_Location :
Seville, Spain
Type :
conf
Filename :
6732377
Link To Document :
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