DocumentCode :
680500
Title :
Hardware co-simulation of Walsh sequences for 3G Software Defined Radio
Author :
Purohit, Gaurav ; Chaubey, V.K. ; Raju, Kota Solomon
Author_Institution :
Dept. of EEE, BITS- Pilani, Pilani, India
fYear :
2013
fDate :
16-18 Dec. 2013
Firstpage :
1
Lastpage :
4
Abstract :
This paper aims the hardware co-simulation of parameterized Walsh code with classical counter architecture using MATLAB SIMULINK based Xilinx System Generator software tools. This is an implementation of the theory which replaces a general Sine and cosine function by set of orthogonal functions such as Rademacher functions and Walsh functions. We investigate 64-orthogonal set for 3G standard such as CDMA2000 and WCDMA with classical binary counter architecture and found that it consumes 28 mW and 130 mW at 100 MHz and 500 MHz respectively. The target FPGA device is Virtex-5 (XC5VLX50T-1ff1136).
Keywords :
3G mobile communication; Hadamard codes; Walsh functions; counting circuits; field programmable gate arrays; software radio; telecommunication computing; 3G software defined radio; 3G standard; CDMA2000; FPGA device; MATLAB SIMULINK; Rademacher functions; Virtex-5; WCDMA; Walsh functions; Walsh sequences; XC5VLX50T-1ff1136; Xilinx System Generator software tools; binary counter architecture; counter architecture; frequency 100 MHz; frequency 500 MHz; hardware co-simulation; orthogonal functions; parameterized Walsh code; power 130 mW; power 28 mW; Computer architecture; Field programmable gate arrays; Generators; Indexes; MATLAB; Multiaccess communication; Radiation detectors; Rademacher function; SDR; System Generator; Walsh function; Walsh sequences;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Control, Automation, Robotics and Embedded Systems (CARE), 2013 International Conference on
Conference_Location :
Jabalpur
Type :
conf
DOI :
10.1109/CARE.2013.6733776
Filename :
6733776
Link To Document :
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