Self-restoring PVT aware independently-controlled Gate FinFET based 10T SRAM cell

As the technology is moving toward nano-scaled device dimensions the Process Voltage and Temperature (PVT) variations have become the dominant agent of increased SRAM failure probability and loss of manufacturing yield. In this paper, we proposed two novel PVT variation aware, independently controlled double-Gate FinFET 10T SRAMcells. Back-gate biasing is exploited to enhanceWrite Margin (WM) and Read Noise Margin (RNM), while built-in feedback mechanism is employed to achieve variation tolerance design during read and standby operations. Proposed cell improve stability by offering stable read and write operations while chip may have different process corners. Three sigma deviations in Static Noise Margin (SNM), RNM and WM due to intrinsic fluctuations alone are projected to demonstrate the stability of cell using 5000 points Monte-Carlo simulations. Compared with the conventional tied-gate 6T cell, the proposed 10T SRAM cells decorate SNM, RNM and WM by 1.9×, 4.7× and 1.6×, respectively. Also, with respect to existing tied-gate 10T SRAM cell, we achieve 6.5% and 20% improvements in RNM and WM, respectively.