Implementing the NASA Deep Space LDPC Codes for Defense Applications

Author

Zhao, Wiley H. ; Long, Jeffrey P.

Author_Institution

MITRE Corp., Bedford, MA, USA

fYear

2013

fDate

18-20 Nov. 2013

Firstpage

803

Lastpage

808

Abstract

Selected codes from, and extended from, the NASA´s deep space low-density parity-check (LDPC) codes are implemented for high speed defense applications. This is part of an effort to build Government reference waveform implementations to assist defense acquisition programs and to promote waveform re-use. Details of the decoder implementation, including memory layout, parallelization architecture, layered-decoding scheduling, and field programmable gate array (FPGA) resource utilization are presented.

Keywords

decoding; field programmable gate arrays; forward error correction; military communication; parity check codes; resource allocation; scheduling; space communication links; FPGA; NASA deep space LDPC codes; NASA deep space low-density parity-check codes; defense acquisition programs; field programmable gate array resource utilization; forward error correction; government reference waveform implementations; high speed defense applications; layered-decoding scheduling; memory layout; parallelization architecture; waveform reusability; Decoding; Digital video broadcasting; Field programmable gate arrays; Measurement; Parity check codes; Random access memory; Throughput; FPGA; Forward Error Correction; Low Density Parity Check Codes;

fLanguage

English

Publisher

ieee

Conference_Titel

Military Communications Conference, MILCOM 2013 - 2013 IEEE

Conference_Location

San Diego, CA

Type

conf

DOI

10.1109/MILCOM.2013.142

Filename

6735722