CADENCE simulation studies on the effect of transistor width size on internal resistance in CMOS rectifier using two PMOS and NMOS

This paper presents studies on the effects of the transistor width size on internal resistance in CMOS rectifier using two PMOS and NMOS configurations. The minimum value of 4 μm widths size of MOSFET in CMOS Rectifier are applied up to maximum value of 1500 μm. The proposed work was designed, modelled and simulated using CADENCE software. The best configuration of the width size on the PMOS and NMOS internal resistance are represented with the lowest internal resistance possible for miniaturizing the CMOS Rectifier. The simulation results are presented to verify the proposed configurations.